To connect a semiconductor chip to a substrate in the related art, a wire bonding method using metal thin lines such as gold wires is widely used. To meet requirements for e.g. higher functions, larger scale integration, and higher speed of semiconductor devices, a flip chip connection method (FC connection method) has been becoming popular, in which a conductive projection called a bump is disposed on a semiconductor chip or a substrate to directly connect the semiconductor chip to the substrate.
Examples of connection between the semiconductor chip and the substrate by the FC connection method also include a COB (Chip On Board) connection method frequently used in BGA (Ball Grid Array), CSP (Chip Size Package), and the like. The FC connection method is also widely used in a COC (Chip On Chip) connection method in which connection portions (bumps and wires) are disposed on semiconductor chips to connect semiconductor chips (see Patent Literature 1, for example).
Packages strongly required for a reduction in size and profile and higher functions increasingly use chip-stack package including chips layered and multi-staged by the connection method above, or POP (Package On Package), TSV (Through-Silicon Via), and the like. Such layering and multi-staging techniques dispose semiconductor chips and the like three-dimensionally, which can attain a smaller package than that in use of techniques of disposing semiconductor chips two-dimensionally. The layering and multi-staging techniques are effective in an improvement in performance of semiconductors and a reduction in noise, a packaging area, and energy consumption, and receive attention as a semiconductor wiring technique of the next generation.
Examples of metals typically used in the connection portion (bumps and wires) include solder, tin, gold, silver, copper, and nickel, and a conductive material containing a plurality of these is also used. The metal used in the connection portion may undesirably generate an oxidized film due to oxidation of the surface of the metal, or impurities such as an oxide may adhere to the surface of the metal to generate impurities on a connection surface of the connection portion. Such impurities, if they remain, may reduce connectivity and insulation reliability between the semiconductor chip and the substrate or between two semiconductor chips to impair the merits of using the connection method described above.
A method for suppressing generation of these impurities includes a method known as an OSP (Organic Solderbility Preservatives) treatment in which a connection portion is coated with an antioxidizing film; however, the antioxidizing film may cause a reduction in solder wettability during a connection process, a reduction in connectivity, and the like.
As a method for removing the oxidized film and impurities, a method for containing a fluxing agent in a semiconductor material has been proposed (see Patent Literatures 2 to 5, for example).